Analysis of Serious Bit Line Failure on 0.19um 64M DRAM with STI Technology

摘要

When 0.19um 64M DRAM was been developing that suffered very serious bit line failure. Because it is the first product with shallow trench isolation (STI) technology in VIS, obviously some previous FA experiences in LOCOS is not applicable to this case. After took much effort, f inally, cross section/plane view TEM and Wright etching analysis show n there were two root causes. 1 That stress induced dislocation in silicon is the major problem witch always occurs at special layout and induced most of the bit line fail (especially long bit line fail). 2) Poly plug residue from impro er IPO1 CMP induced bit line fail