Low-Cost Wafer Level Packaging Process

摘要

Today, semiconductors are being connected to other components of the system through three main interconnect technologies - Wirebond, TAB and Solder bump. Of the three technologies, use of solder bump provides the lowest impedance electrical path and a higher I/O density as compared to wirebond and TAB. Wafer bumping is often accompanied by a need for redistribution of the current carrying pads on the silicon in order to reduce the substrate cost and better manufacturing yields. Besides, there is a need to deposit a metallic layer (Under Bump Metallization) underneath the bump for good reliability of the packaged system. The two widely used processes used for depositing a thin metal film, either for redistribution or UBM are Physical Vapor Deposition (sputtering) and evaporation. These processes are significant contributors to the cost of the bumped wafer. In the packaging industry, there is also a drive for going towards wafer level packaging solutions in order to minimize the packaging cost and giving high production rates. This paper describes the development of a new wafer level process which minimizes the cost of the bumped wafer that requires redistribution of its bond pads and at the same time, offers the advantages of a wafer level packaging solution. The process is based on the concept of a build up technology that channels the bond pads to a large pitch array in order to make the interconnection to the board. The packaging technology will be suited for high frequency, small size, light weight applications. This process has the potential to drive the industry away from wire bonding to a one step wafer level interconnection process. The paper also provides the results of the characterization that was performed on the package.