Sub-22 nm silicon template nanofabrication by advanced spacer patterning technique for NIL applications

摘要

A spacer patterning technique using a poly-Si micro-feature and a SiO_2 spacer has been demonstrated to achieve sub-22 nm structures with conventional semiconductor equipments. The sub-22 nm structures have been fabricated by a plasma etching of Si substrate with a spacer oxide mask of which dimension is accurately controlled by the deposited film thickness. The profile of the Si nano-feature was influenced by an O_2 flow rate during Si etching in inductively coupled plasma (ICP). As the O_2 flow rate was decreased, the etch profile was improved vertically even though the etch rate of Si was slightly decreased. We obtained a 6-inch Si template with both nano- and micro-features of positive shape used for a master mold in nanoimprint lithography (NIL). The nano-sized Si features showed 22-nm width and 145-nm height with the slope of 87°. Further size reduction by anisotropic wet etching with KOH solution was also investigated.