Department of Electrical and Computer Engineering, University of New Hampshire, Durham, 03824, USA;
Department of Electrical and Computer Engineering, Stony Brook University, NY 11794, USA;
Department of Electrical and Computer Engineering, Stony Brook University, NY 11794, USA;
Department of Electrical and Computer Engineering, Stony Brook University, NY 11794, USA;
Department of Electrical and Computer Engineering, University of New Hampshire, Durham, 03824, USA;
Integrated circuits; Three-dimensional displays; Logic gates; Reverse engineering; MOS devices; Transistors; Two dimensional displays;
机译:逻辑锁定和IC伪装方案的近似弹性
机译:使用铁电FET进行硬件安全性栅极级逻辑迷路和运行时间重新配置的实验演示
机译:单片式 - 3D(M3D)互补金属氧化物半导体 - 纳米机电(CMOS-NEM)混合可重构逻辑(RL)电路
机译:单片3D IC安全晶体管级伪装逻辑锁定方法
机译:迈向安全逻辑锁定以加强硬件安全性
机译:考虑无连接FET的单片3D逻辑电耦合的电路仿真
机译:评估相关功率分析(CPA)攻击晶体管级逻辑锁定的弹性
机译:GpU和多核CpU上3D恒定系数模板的块迭代方法。