Method for transistor-level calculation of the precharge time of domino logic circuits with unlocked evaluation paths

摘要

According to the present invention, a method is provided for transistor level calculation of the precharge time of a domino logic circuit. In one version of the invention, the domino logic circuit has a plurality of cascaded stages, at least one stage having an unclocked evaluation path. In this version, the method includes the steps of determining a reset time for at least one stage of the domino circuit, determining a total reset time for the stages upstream of the at least one stage, and summing the reset time of the at least one stage with the total reset time of the cascaded stages upstream of the at least one stage to determine the precharge time. In another version, the method includes the step of performing a circuit analysis of the channel connected transistors in the at least one stage having an unclocked evaluation path.