Integrated power supply packaging technique with reduced parasitic inductance for on-die voltage regulator design and application

摘要

On-die voltage regulator can improve load regulation, facilitate power management, reduce crosstalk, eliminate transient spikes, and save the board space as well as interconnect pin-counts. This paper presents an integrated circuit package design that provides a low inductance power supply with the capacitive stabilizer for an on-die voltage regulator. A novel 3D design using layered inter-digitated structure is composed of inter-leaved power and ground tracks configured to introduce the negative mutual inductive coupling in between. This design leads to significant reduction of the total parasitic loop inductance, which is verified by electromagnetic simulation using Ansys Q3D. The voltage drop simulated by Spice models is also greatly improved using the proposed layered inter-digitated structure.