首页> 外文会议>2014 IEEE Workshop on Electronics, Computer and Applications >Utilizing micro-architecture parallelism to hide reclaiming operations for NAND multi-channel SSDs
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Utilizing micro-architecture parallelism to hide reclaiming operations for NAND multi-channel SSDs

机译:利用微架构并行性隐藏NAND多通道SSD的回收操作

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Due to the unique erase-before-write characteristic of flash memories, flash-based solid-state disks (SSDs) use out-of-place update and require a garbage collection process to recycle invalid data space. This process brings extra operations and latencies, causing I/O blocking and performance degradation, especially when the device is close to be full. In this work, we use a parallel-unit-aware allocation policy for the internal migrating write and incoming requesting write, scheduling and packing all the operations together to utilize the micro-architecture parallelism of multi-channel SSDs. Trace-driven simulations reveal that the proposed design reduces 33.31% of response time, on average, thus improves the device performance.
机译:由于闪存具有独特的写前擦除特性,因此基于闪存的固态磁盘(SSD)使用原位更新,并需要进行垃圾回收过程以回收无效的数据空间。此过程会带来额外的操作和延迟,从而导致I / O阻塞和性能下降,尤其是在设备快要装满时。在这项工作中,我们对内部迁移写入和传入请求写入,将所有操作调度和打包在一起使用并行单元感知分配策略,以利用多通道SSD的微体系结构并行性。跟踪驱动的仿真表明,提出的设计平均减少了33.31%的响应时间,从而提高了器件性能。

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