Estimation of process-induced variations in double-gate junctionless transistor

摘要

In this paper, the impact of process induced variations on the electrical characteristics of a junctionless symmetric double-gate transistor (DGJLT) is reported for the first time. The process parameters considered here are gate length (L), thickness of silicon film (Tsi) and gate oxide thickness (Tox). The impact of these process parameters on the electrical parameters viz., ON current, threshold voltage (VT) and subthreshold slope (SS) are systematically investigated with the help of extensive device simulations and compared with conventional symmetric doublegate transistor (DGMOS). It is seen that ON current variation with silicon thickness is higher for DGJLT compared to DGMOS. Threshold voltage of DGJLT is more sensitive to silicon thickness and gate oxide thickness as compared to DGMOS. The overall SS variation is negligible in DGJLT compared to DGMOS.