SOI CMOS Compact Modeling based on TCAD Device Simulations

摘要

The aggressive product development schedules demanded by today's marketplace require that early circuit design work overlaps substantially with process development activity. To support this, device models must be available prior to fabrication of the finalized CMOS device design. This work describes a Technology Computer Aided Design (TCAD) -based methodology for generating compact models in advance of hardware availability. The exercise was performed on a 65nm node SOI CMOS technology. TCAD was used in the conventional way to extrapolate interim CMOS devices to target performance by simulating planned process improvements. The resulting TCAD simulations were used to generate Ⅰ-Ⅴ and C-V data for compact model extraction. The extracted model is compared with TCAD simulations and the fit is shown to be good.