Optimal metrology sampling strategies for AEC/APC Applications

摘要

Introduction With shrinking process windows and smaller device geometries in semiconductor manufacturing, the need to accurately monitor within-wafer spatial variations becomes increasingly critical. This is both in the contexts of statistical process control (SPC) for process regulation, and monitoring for low latency detection of process drift. Monitoring within wafer variability requires CD measurements at multiple sites across a wafer. However, the capital, operating, and cycle-time costs associated with metrology options limit the scope of process monitoring. Total-cost-aware optimization of metrology sampling schemes becomes economically critical. An effective sampling strategy enables effective process control while containing metrology costs. Therefore, the effectiveness of a sampling scheme depends intimately on the process control objective. Optimal measurement resource allocation to address process variability been studied in [1,2].