CORRIGIBLE COMPARATOR FOR TRIPLE MODULAR REDUNDANCY CELL

摘要

The invention is directed to a corrigible comparator (100). The comparator comprises a data-forwarding stage configured to provide in dependence on a clock-based forwarding trigger event a first comparison binary value (Ax) that is correlated to a current binary value of input binary data signal (D). In a comparison stage, this value is compared to an external second comparison binary value (Bx) and an output binary value (Qx) that is correlated to the first comparison binary value (Ax) is provided when the compared values are identical. A feedback binary value (SCx) correlated to the first comparison binary value (Ax) is provided. A correction stage (Fx) is configured to receive external feedback binary values (SCy, SCz) and, depending on a correction trigger event, to provide to the comparison stage a corrected binary value (Ax') correlated to the feedback binary values when they have the same binary value.