PROGRAMMING MEMORY CELLS USING CODED TLC-FINE

摘要

A memory device including control circuitry communicatively coupled to non-volatile memory and configured to receive a parity bit stored using a data structure and to receive a first subset of host data that includes block data related to a set of memory cells . The control circuitry may be configured to perform a read operation to identify a second subset of host data that includes additional block data related to the set of memory cells. The control circuitry may be configured to decode the second subset of host data using the parity bit. The control circuitry may be configured to perform a write operation to write the block data to at least one or more memory cells that are part of the set of memory cells.