METHOD FOR HIGH PERFORMANCE STANDARD CELL DESIGN TECHNIQUES IN FINFET BASED LIBRARY USING LOCAL LAYOUT EFFECTS (LLE)

摘要

The inventive concept describes a method for high-performance standard cell design techniques in FinFET-based libraries using local layout effect (LLE). The inventive concept describes a manufacturing process using a standard FinFET cell layout with double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one exemplary embodiment, the method includes removing one or more fingers of a P-type FinFET (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a half-diffusion break (Half-DDB) is introduced on the N-type FinFET (NFET) side inside the cell boundary using a cut-poly layer. The cut-poly layer isolates the PFET and NFET gates as well as becomes part of the hybrid structure. In addition, the removed one or more fingers of the PFET gates are converted to two floating PFET gates by shorting the drain and source terminals of the PFET gate to a common voltage net.