ELMORE DELAY TIME (EDT)-BASED RESISTANCE MODEL

摘要

We disclose an integrated circuit design tool for modeling resistance of a terminal of a transistor such as a gate, a source, a drain, and a via. A structure of the terminal is specified in a data structure in memory using a three-dimensional (3D) coordinate system. For each of a plurality of volume elements in the specified structure, an Elmore delay time (EDT) is determined. For those volume elements in the plurality of volume elements that are located on a surface of the gate terminal which faces the channel region, an average EDT (aEDT) is determined based on the EDT. Point-to-point resistance values of the terminal are generated as a function of the aEDT and a capacitance of the terminal.