A conductive via layer is deposited on the bottom electrode, patterned and trimmed to form sub 20 nm conductive vias on the bottom electrode. The conductive via is encapsulated with a first dielectric layer that is planarized to expose a top surface of the conductive via. The MTJ stack is deposited on encapsulated conductive vias, wherein the MTJ stack includes at least a pinned layer, a barrier layer and a free layer. A top electrode layer is deposited on the MTJ stack, patterned and trimmed to form a sub-30 nm hard mask. The MTJ stack is etched using a hard mask to form the MTJ device, over etched into the encapsulation layer but not into the bottom electrode, where the metal re-deposition material is encapsulated at the bottom of the MTJ device. It is formed on the sidewall of the layer, but not on the sidewall of the barrier layer of the MTJ device.
展开▼