Asynchronous clock generation for time interleaved successive comparison analog to digital converters

摘要

A clock generator (500) is a first input (502) for receiving a global clock signal (216), a second input (504) for receiving a completion signal (516), and a differential output (116, 312, 31) from a comparator (212) in a conversion cycle A third input (506) for receiving 4 is provided.The clock generator (500) generates a control clock signal (226) at least in part on the global clock signal (216) and the differential outputs (116, 312, 314) and the control clock signal (226) for the next conversion cycle is compared to a comparator (212) Also includes a logic circuit (508) configured to provide.The logic circuit (508) is also configured to disable the control clock signal (226) in response to a completion signal (516) indicating completion of the necessary conversion cycle in the conversion stageSelection diagram