Circuit arrangement for the selection of a pulse sequence of a plurality of pulse sequences of a pulse sequence group in electronic waehlsystemen

摘要

784,901. Automatic exchange systems. POSTMASTER GENERAL. Jan.. 18, 1954 [Jan. 20, 1953; April 14, 1953], Nos. 1684/53 and 10220/53. Class 40 (4). A pulse train is selected from amongst a plurality of such trains and its identity is registered on a plurality of registering devices which are operated in different combinations, e.g. two at a time. Alternatively the registering devices (of which there are, say, n) may be operated in combinations of different numbers, i.e. the combinations may be taken n at a time, n - 1 at a time ... 1 at a time giving a total of 2SPn/SP - 1 combinations. Fig. 1 (1684/53) illustrates the equipment to which the invention is applied. Circuits are represented by leads such as CT1 connected to a multiplexing arrangement MX1 which produces an output pulse in an appropriate time position provided the circuit is not marked unavailable over the inhibiting lead DSL1. The pulses then pass through an inhibiting gate PSG1 which may take effect if the pulses at that particular time position are not required to be selected. The pulse train is then applied perhaps together with others to a selector SEL1 which is required to select one of them, indicate its identity by marking a combination of leads DCIL and also to produce a pulse train coincident therewith over the lead PIL1 In a first embodiment, Fig. 2 (1684/53), the n registers are operated in combinations two at a time. To this end pulse leads such as PL2, PL3 are provided carrying combinations of pulse trains so arranged that each pulse train to be registered coincides with pulse trains in a unique combination of two of these leads. It is assumed that the pulse train received on the input lead PFL1 coincides with trains in leads PL2, PL3. The incoming pulse operates a device BD1 such as a blocking oscillator which accordingly emits a pulse and then remains unresponsive to any further incoming pulses for a prescribed period. The pulse is then fed to a plurality of coincidence gates such as PCG1, PCG2, which are enabled by pulses on an associated pair of leads PL2, PL3. Small delay lines TD1, TD2 inserted in these leads, allow for the slight delay introduced by the device BD1. The outputs of the coincidence circuits operate a pair of registers REG1, REG2 which may be gas-filled tubes. These produce corresponding D.C. indications on a pair of leads DCIL1, DCIL2. For producing the output pulse, the registers have associated gates PG1, PG2 which they open to pass corresponding combinations of pulse trains from PL2, PL3 to a coincidence circuit PCG3 whose output thus consists of the required pulse train. A multiplexing arrangment (MX1, Fig. 1) for use in conjunction with the above system is also described, Fig. 4 (1684/53), in which the modulation is effected in two stages. The leads A ... E carry combinations of pulse trains similar to those of PL2, PL3 above. It will be observed that the multiplex inputs L4, L5 whose corresponding pulses are obtained by combining pulse trains on A, B and A, E respectively are first caused to modulate pulses B, E respectively in gates PCG4, PCG5, whose outputs are then combined for application to gate PCG9 which is opened by pulse trains on lead A. Similar groupings are effected for inputs L6 ... L8 and so on, whose corresponding pairs of leads contain a common lead B, C .... In a second embodiment, Fig. 2 (10220/53), combinations of any number (including one) of registers may be used. As shown, three registers are used to record up to seven pulse trains. To this end three leads PL11 ... PL13. are provided in which each pulse train occurs either on one lead only or on combinations of two leads or on all three leads, e.g. as illustrated in Fig. 1 (10220/53). The circuit leads CT1 ... CT7 are applied via disabling gates to coincidence gates PG1 ... PG7 fed over combinations of operating and inhibiting leads connected to PL11 ... PL13 to produce output pulses on lead PL1 indicative of available circuits. This corresponds to the multiplex MX1, Fig. 1 (1684/53). The pulses then pass through a further inhibiting gate to the blocking oscillator or like device BD1 which operates to one of the pulses whereafter it remains unresponsive for a prescribed time. The output is then fed to gates PCG1 ... PCG3 fed by pulse trains from leads PL11 ... PL13 via delay lines D1 ... D3 which compensate for the delay in the operation of the blocking oscillator BD1. Coincidences occur in unique combinations in these gates to operate corresponding registers REG1 ... REG3. The selected pulse train is thereby indicated by D.C. on the corresponding register output leads DCIL1 ... DCIL3. These outputs may be combined on lead SL2 to further inhibit the operation of the blocking oscillator until the register is restored. The pulse train coincident with the selected train may then be produced from the D.C. markings on DCIL1 ... DCIL3 by the circuit shown in Fig. 5 (10220/53). A marking on any DCIL lead inhibits gate SG23 and hence PSG11 unless its associated PL lead is pulsed. Thus pulses can only emerge from PSG11 if they are coincident on all PL leads whose DCIL leads are marked. If, however, the pulse is also present on a PL lead whose DCIL lead is unmarked this pulse passes through SG22 to prevent the appearance of the pulse on the output of PSG11. A detailed circuit for this arrangement is given, Fig. 6 (10220/53) (not shown). In an arrangement providing a D.C. marking on a single lead indicative of the selected pulse train, the DCIL leads connected to inhibiting and operating leads in various combinations to gates DCG1 ... DCG7, Fig. 7 (10220/53), to provide a D.C. output on one of the leads DCIL11 ... DCIL17. Specifications 722,179 and 781,916 are referred to.