LOGIC CIRCUITS FOR PROCESSING BINARY SIGNALS TO SOLVE BOOLEAN FUNCTIONS

摘要

1466466 Logic circuit SIEMENS AG 18 April 1974 [26 April 1973] 17153/74 Heading G4A A logic circuit solves Boolean functions involving AND and OR operations on a series of binary signals in accordance with instructions specifying AND and OR operations and, includes a first bi-stable circuit 1 set by binary "1" signals and reset by binary "0" signals, a second bi-stable circuit 2 set by a binary zero signal, arranged when set to block the subsequent setting of the first bi-stable, and arranged to be reset by an OR instruction, a third bistable circuit 3 set by an OR instruction if the first bi-stable is set, and an OR gate 8 providing an output in response to the states of the first and third bi-stable circuits. Two embodiments are described. In both cases a series of binary signals a-n are presented in parallel and are clocked to the first bi-stable 1 in series via line LL by pulses L a -L n and clock T. An instruction signal V is supplied between the supply of the binary signals, V = 1 indicating an OR operation and V = 0 an AND operation. In the first embodiment given an AND operation gate 7 is blocked and bi-stable 1 is set by binary 1 signals. Should a 0 signal occur bistable 1 is reset, and bi-stable 2 is set thus preventing, via gate 4, bi-stable 1 from being set by subsequent binary signals. The AND function is thus fulfilled. If an OR instruction occurs, V = 1, bi-stable 2 is reset so that a subsequent binary "1" signal may set bi-stable 1. Further gate 7 is enabled so that if bi-stable 1 is set, indicating a preceding fulfilled AND condition or a preceding single binary 1 following an OR instruction bistable 3 is set. The output 9 is derived from OR gate 8 and the circuit thus solves functions such as: in the form: The second embodiment Fig. 2 (not shown) is arranged to deal with parentheses and includes an up-down counter which counts up one for each opening bracket and down one for each closing bracket. The contents of the counter are fed into a store both when an OR instruction occurs and bi-stable 1 is set, and when a binary "0" signal occurs. A comparator provides signals when the count in the counter is less than and equal to that in the store, the signals being used selectively to reset bi-stables 2 and 3 to take account of parentheses. Within a single bracket pair parentheses are imposed as in the first embodiment, i.e. A AND B OR C is given as (A AND B) OR C.