PARALLEL CODER FOR PULSE CODED TRANSMISSTION WITH A COMPRESSION LAW

摘要

1418848 Analogue-to-digital conversion COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 14 Sept 1973 [14 Sept 1972] 43332/73 Heading H3H An analogue to digital converter having a compression law defined by successive linear segments of progressively decreasing slope for converting an input analogue N into a parallel code comprising a sign bit S, bits A, B, C defining the segment in which the input lies, and bits W, X, Y, Z defining the position of the input within the segment, comprises an input circuit, Fig. 2a, having non-linearly related threshold circuits A10-A14 for generating S, A, B and C, and an output circuit, Fig. 5, having threshold circuits A31-A45 supplied with linearly spaced reference levels from a potential divider 30 energized with current J of a sign and value selected according to a non-linear relationship in dependence on the outputs of threshold circuits A10-A14. As shown, one of four input amplifiers Al- A4 having respective gains of 1, 8, 8 plus positive bias, and 8 plus negative bias, is switched in according to the outputs of threshold circuits A10-A14, remembered in flip-flops B 10 -B 14 . The bias of amplifiers A3, A4 is equivalent to the upper end of the lowest segment of the compression law. The reference current J for the circuit of Fig. 5 is obtained in a non-linear decoder (Fig. 4, not shown) which selects one of four tapping points (e ... h) on a geometrically progressive voltage divider according to the outputs of flip-flops B11-B14, the voltage divider being energized with positive or negative current depending on the sign bit S.