By means of support is constructed from two half adders errors reliable full adder in cml - art

• 1. 能够支持加法和减法的加法器和支持加法和减法的方法 [P] . 中国专利： CN103970503B . 2019.03.01
• 2. 能够支持加法和减法的加法器和支持加法和减法的方法 [P] . 中国专利： CN103970503A . 2014-08-06
• 3. of binary half-adders and from binary half adders constructed, full adder acting in parallel [P] . 德国专利： DE1080329B . 1960-04-21

  机译： 二进制半加法器和从二进制半加法器构成的全加法器并行运行

• 4. Digital circuit arrangement and hence constructed half - and full adder [P] . 德国专利： DE2741848A1 . 1978-03-23

  机译： 数字电路装置，因此构成了半加法器和全加法器

• 5. Circuit arrangement and method for the calculation of digital sums into a half conductor by means of support parallel adder with [P] . 德国专利： DE3940897C2 . 1999-05-12

  机译： 借助支持并行加法器计算数字和为半导体的电路装置和方法

• 1. A Low-Area, Low-Power Dynamically Reconfigurable 64-Bit Media Signal Processing Adder [J] . Priscilla Sharon Allwin, Chien-In Henry Chen 电脑和通信（英文） . 2021,第003期
• 2. Research of magnetic self-balance used in a repetitive high voltage rectangular waveform pulse adder [J] . Qianyu ZHOU, Liqing TONG, Kefu LIU 等离子体科学和技术（英文版） . 2018,第001期
• 3. Numerical Simulation of Azimuthal Uniformity of Injection Currents in Single-Point-Feed Induction Voltage Adders [J] . WEI Hao, SUN Fengju, YIN Jiahui, 等离子体科学和技术（英文版） . 2015,第003期
• 4. Probabilistic Error Modeling for Two-part Segmented Approximate Adders [C] . D. Celia, Vinita Vasudevan, Nitin Chandrachoodan IEEE International Symposium on Circuits and Systems . 2018
• 5. High-speed carry skip adder implemented using speculative Han-Carlson parallel prefix adder. [D] . Narayanaswamy, Rakesh. 2016
• 6. Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders [O] . P. Balasubramanian, S. Yamashita -1
• 7. Incorporation of Reduced Full Adder and Half Adder into Wallace Multiplier and Improved Carry-Save Adder for Digital FIR Filter [O] . S. Chinnapparaj, D. Somasundareswari 2016

• 1. New Binary Modular Adder Tree Structure for Error Checker of Arithmetic [J] . Mingda Zhang ,Shugang Wei . 通讯和计算机 . 2013,第003期
• 2. 经典游戏外设里程碑Razer Death Adder炼狱蛙蛇 [J] . 史洪绪 Mac.Lan . 微型计算机 . 2015,第6期
• 3. 32位全静态加法器的电路优化 [C] . 雷丛华 ,李振涛 ,李少青 . 第九届计算机工程与工艺全国学术年会 . 2005
• 4. 一款DSP硬核中加法器的全定制设计 [A] . 刘骁 . 2012