installation of data processing with a new preparation and execution of computer instructions

摘要

One editing processor and one executive processor (EP) each are provided which are jointly controlled from a loadable microprogram memory (WCM), the first processor remaining autonomous due to a separate detail control (ZS-ROM). Thus, both processors can jointly use one interface to the memory system (ASP) and one set of internal general registers (MA, MD) without mutually impeding each other. Since the editing processor only provides register operands or effective memory addresses of a subsequent machine instruction, register or memory conflicts can be solved in a simple manner with the aid of comparison devices (SV1, SV2 and RV1, RV2) for memory and register addresses. The editing processor takes over the reading of instructions and the calculation of addresses and the executive processor takes over the execution of instructions. A configuration of the type described is considered particularly in medium-capacity commercial data processing systems. IMAGE