A programmed digital secondary clock which functions as a master clock, a sub-master clock or a slave clock. The master clock maintains an updated real time count based on a 50 hz or 60 hz ac line or digital oscillator signal, displays the count, and serially transmits digital information representative of the updated real time count for use by a slave clock. The sub-master clock, receives an hourly or twice-a-day correction signal from a conventional master clock or a conventional electronic receiver, corrects the real time count, displays the corrected count, and serially transmits digital information representative of the corrected real time count for use by a slave clock. Identical programmed digital secondary clocks can be connected in daisy chain. The first clock can operate as a master clock or as a sub-master clock. The following clocks can be operated as slave clocks. The slave clock, receives serial digital information representative of real time every second, maintains an updated real time count based on the received information, displays the count, and serially transmits digital information representative of the real time count for use by a following slave clock. The programmed digital secondary clock can be operated as an elapsed timer or as an interval timer without interfering with the operation of the clock as a master, sub-master or slave clock.
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