Coherent control of information in hierarchy of memories - ensures optimum control of data in different speed processors

摘要

The management of a hierarchy of data memories ensures optimum conditions for speed of access where memories are faster than those adjacent in the hierarchy. The slowest are used for storage of data which is not modified while the faster contain modifiable data. A processor is contained in a hierarchy of processors which are slower or faster in operation. At this level the contents of a data block are addressed and are read and written under control of a control processor with associated index. This processor communicates with processors and their index registers at other levels. Areas in the index registers and reading writing register are separately identified and addressed in order that the contents may be incremented or decremented providing timing for the appropriate processor.