首页> 外国专利> Dynamically variable electronic delay lines for real time ultrasonic imaging systems

Dynamically variable electronic delay lines for real time ultrasonic imaging systems

机译:用于实时超声成像系统的动态可变电子延迟线

摘要

A dynamically variable electronic delay line for real time ultrasonic imaging systems is disclosed so as to controllably phase the signals associated with an array of electro-mechanical transducer elements and thereby enable the selective scanning and dynamic focusing of a target. A controllable variable electronic time delay apparatus is coupled to each of the electromechanical transducer elements of the array and in one embodiment thereof constitutes an electronic memory having separate write- in and read-out addressing capabilities. The signals associated with a respective ultrasonic transducer element are fed in at selected write-in addresses and subsequently read- out and extracted after an initial time delay interval. The write-in and read-out address pointers of the memory are continuously sequenced during operation of the device and the time delay interval is a function of the difference between the addresses, as well as the clock rate. The initial delay can be varied by instantaneously modifying either the write-in or the read- out address pointer during the sequencing thereof, such modification being defined as an "edit-splice" technique. In other embodiments of the invention, the time delay apparatus could comprise a multiple cell memory or register in which a plurality of signals from an associated transducer element are stored and subsequently read-out after an initial time delay, which delay can be changed either by varying the effective length of the shift register or by varying the clock rate at which the shift register advances the signals stored therein, or through an "edit-splice" technique as above-described.
机译:公开了一种用于实时超声成像系统的动态可变的电子延迟线,以便可控地对与机电换能器元件的阵列相关联的信号进行相位调整,从而实现目标的选择性扫描和动态聚焦。可控的可变电子时间延迟装置耦合到阵列的每个机电换能器元件,并且在其一个实施例中构成具有单独的写入和读出寻址能力的电子存储器。与相应超声换能器元件关联的信号在选定的写入地址处馈入,然后在初始时间间隔后读出并提取。存储器的写入和读出地址指针在设备运行期间连续排序,延时间隔是地址之间的差异以及时钟速率的函数。可以通过在序列化过程中瞬时修改写入或读出地址指针来改变初始延迟,这种修改被定义为“编辑拼接”技术。在本发明的其他实施例中,时间延迟装置可以包括多单元存储器或寄存器,其中存储了来自相关联的换能器元件的多个信号,并且随后在初始时间延迟之后被读出,该延迟可以通过以下方式改变:改变移位寄存器的有效长度,或者通过改变移位寄存器使存储在其中的信号前进的时钟速率,或者通过如上所述的“编辑拼接”技术。

著录项

  • 公开/公告号US4173007A

    专利类型

  • 公开/公告日1979-10-30

    原文格式PDF

  • 申请/专利权人 SEARLE G D &;

    申请/专利号US19770812109

  • 发明设计人 RONALD E. MCKEIGHEN;MICHAEL P. BUCHIN;

    申请日1977-07-01

  • 分类号G01S9/66;

  • 国家 US

  • 入库时间 2022-08-22 19:15:08

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号