Integrated CMOS circuit for signal level control - has two MOS transistors with N and P channels connected in series, and diode biassing circuit between their gates

摘要

The circuit is mounted at a junction between binary switching networks with low signal amplitude, such as TTL circuits, and switching circuits with large signal amplitudes, such as integrated CMOS circuits. It has an MOS transistor of the enrichment type. The channel transmission paths are connected in series between the terminals of a supply voltage source, and their junction point serves as the output. A diode circuit generating a constant voltage drop (U) and carrying a very small current in the /uA range is inserted between the gates of the two transistors (TN1, TP1). It shifts the input level at the transistor (TP1) gate w.r.t. the input signal lever, so that transistor (TP1) is reliably blocked by the input signal higher level.