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Clock-pulse train monitoring circuit - compares input clock pulse train pattern with stored control train pattern to detect differences
Clock-pulse train monitoring circuit - compares input clock pulse train pattern with stored control train pattern to detect differences
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机译:时钟脉冲序列监视电路-将输入时钟脉冲序列模式与存储的控制序列模式进行比较以检测差异
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摘要
The monitoring circuit has a single test line (b) connected to the clock pulse output lines (A1, An), in order to detect faults in the time sequence of the pulse trains appearing on these lines. The pulse sequence on the test line is compared (Vg) with the time characteristics of the control signals of fixed format used for originally generating these pulses. If there is a difference in a characteristic (time at which a pulse or pulse interval occurs, a fault signal is transmitted (GD, GA, GZ). The system enables monitoring of clock pulse train on a single line, one which the actual pulse trains are fed to the components.
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