首页> 外国专利> Test circuit for time demultiplexer - compares test words in memory with same test words passed via demultiplexer to address memory

Test circuit for time demultiplexer - compares test words in memory with same test words passed via demultiplexer to address memory

机译:时间解复用器的测试电路-将内存中的测试字与通过解复用器传递到地址存储器的相同测试字进行比较

摘要

The test circuit has the n outputs (al-an) of the address-controlled time demultiplexer (DEM) connected to the n inputs of a test memory (D, Sp). The demultiplexer's address input receives test words which are also stored in the memory's storage cells (Z1 etc). The test words are their own addresses in the memory. Initially the demultiplexer's signal input receives a 'l' signal. The test word stored in the memory at the selected cell is compared with the test word applied to the demultiplexer as address. If the two words are not the same an error signal is released indicating that the demultiplexer is not distributing its signals correctly.
机译:测试电路的地址控制时间解复用器(DEM)的n个输出(al-an)连接到测试存储器(D,Sp)的n个输入。解复用器的地址输入接收测试字,这些测试字也存储在存储器的存储单元(Z1等)中。测试字是它们在存储器中的地址。最初,解复用器的信号输入接收一个“ l”信号。将存储在所选单元中的存储器中的测试字与作为地址施加到解复用器的测试字进行比较。如果两个字不相同,则释放错误信号,指示多路分解器未正确分配其信号。

著录项

  • 公开/公告号DE2851903A1

    专利类型

  • 公开/公告日1980-06-12

    原文格式PDF

  • 申请/专利权人 SIEMENS AG;

    申请/专利号DE19782851903

  • 申请日1978-11-30

  • 分类号H04J3/14;

  • 国家 DE

  • 入库时间 2022-08-22 17:34:18

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