PURPOSE:To generate an arbitrary gross start-stop distortion and to measure the margin of a communication device, by using a frequency division circuit which frequency-divides a clock with a set frequency-dividing ratio, changing the length of start bit and stop bit of the start-stop synchronous data and generating an arbitrary gross start-stop distortion. CONSTITUTION:When a data transmission circuit 6 is started after a data (j) is latched to a latch circuit 1, a start bit ST is transmitted, the trailing edge is detected at a start bit detection circuit 7 and its output (b) resets a frequency division circuit 3 and a latch circuit 5. A selector 2 selects a start bit length data (d) with an output (i) of the latch circuit and applies the data to the circuit 3 and a data bit number data (h) is preset to a counter 4. The circuit 3 counts a clock (g) for a period corresponding to the bit length of the data (d), generates an output (c) and the transmission circuit 6 transmits the 1st bit. When the content of count of the end of start bit transmission is latched to a latch circuit 5, the selector 2 adds a data bit length data (f) to the circuit 3 to generate a prescribed bit length.
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