Shift register latch circuit means contained in LSI circuitry conforming to level sensitive scan design (LSSD) rules and techniques and utilized at least in part for check and test purposes

摘要

LSI circuitry conforming to LSSD rules and techniques usually requires at least a small portion of circuitry used only for check and test purposes.PPThe disclosed circuitry meets the LSSD design rules and techniques and considerably reduces the test circuit overhead. The disclosure modifies the known shift register latch (SRL) strategy by logically removing the master latches from the slave latches and by providing the slave latches with multiple shift inputs, e.g., two shift inputs (FIG. 2). The LSSD shifting philosophy remains unchanged to the extent that at the time of shifting, the virtual (not available slave latch) becomes real (physical) by assigning the only physical slave latch to the respective master latch. The present disclosure provides for multiple master latches to be dynamically assigned to one slave latch during shifting. This is in contrast to the known SRL chain approach requiring one slave latch for each master latch. Level Sensitive Scan Design Rules and Techniques are extensively disclosed in the testing art. See for example (1) U.S. Pat. No. 3,783,254 entitled "Level Sensitive Logic System" filed Oct. 16, 1972, granted Jan. 1, 1974 to E. B. Eichelberger, of common assignee herewith, or; (2) "A Logic Design Structure for LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, pages 462-468, June 20, 21 and 22, 1977, New Orleans, Louisiana, IEEE Catalog Number 77, CH1216-1C.