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MULTIPLYING CIRCUIT FOR ELEMENT BELONGING TO GALOIS FIELD GF (2M)

机译:加洛伊斯菲尔德GF(2M)的元素倍增电路

摘要

PURPOSE:To perform the arithmetic processing at a high speed by using a shift register connected to a primitive irreducible polynomial for a Galois field of GF (2m), a microprocessor and its subordinate RAM, etc., to constitute a multiplying device. CONSTITUTION:For a shift register 1 connected to a primitive irreducible polynomial of GF (24), the lowest order is regarded as X0=1 and then as X1, X2 and X3 toward the higher orders. Then the register 1 is sent toward the highest order from the lowest one when a clock CLK is applied via a lead wire 4. When X4 is obtained with transmission of X3, the X4 is written to X0=1. At the same time, the value with which the X0=1 is sent and the output received from the X4 are calculated by an exclusive OR circuit 11 and the result of this calculation is written to the X1. A microcomputer 2 contains a CPU, a RAM and a ROM together with a multiplicand register area 21, a multiplier register area 22 and a result register area 23. Thus the register 1 connected to the primitive irreducible polynomial is actuated for fast production of a desired polynomial.
机译:目的:通过使用连接到GF(2 )的Galois字段的原始不可约多项式的移位寄存器,微处理器及其从属RAM等来高速执行算术处理,以构成乘法装置。组成:对于与GF(2 <4>)的本原不可约多项式连接的移位寄存器1,最低阶为X <0> = 1,然后为X <1>,X <2>和X <3 >向更高的顺序。然后,当通过导线4施加时钟CLK时,寄存器1从最低位向最高位发送。当通过传输X <3>获得X <4>时,X <4>被写入X <0> = 1。同时,通过异或电路11计算发送X <0> = 1的值和从X <4>接收的输出,并将该计算的结果写入X <1> 。微型计算机2包括CPU,RAM和ROM以及被乘数寄存器区域21,乘数寄存器区域22和结果寄存器区域23。因此,致动与原始不可约多项式连接的寄存器1以快速产生期望的多项式。多项式。

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