Method and arrangement for exchanging data words between two memories, for example the buffer of a byte multiplex channel and the buffer of the input/output command unit of a higher level of a data-processing system

摘要

1. A method of exchanging data words between two stores, e.g. the buffer store (BYMST) in a byte multiplex channel (CHn) and buffer store (MMD) of the superordinate input/output control unit (IOC) in a data processing system, in the one or other direction in dependence upon commands of a microprocessor control unit (DPV-ST) with a constant duration of the individual operating cycles (EO), characterized in that in the case of data transfers (TB) which cannot be executed by one operating cycle (EO) because of excessive delay times (LF) between the microprocessor control unit (DVP-ST) with the first store (MMD) and the remote second store (BYMST) and/or operating times of the second store, the execution is divided into a plurality of transfer phase (PH1 to PH3) and the various transfer phases (PH1 to PH3) are triggered by various, consecutive operating cycles (e.g. EO1 to EO3) of the microprocessor control unit (DVP-ST), and that all the transfer phases (PH1 to PH3) are each controlled by a phase control pulse (T) which is derived from the respective operating cycle (EO) with a fixed phase position in relation thereto and each results in the storage or intermediate storage of the items of information made available in the previous transfer phase, so that the various transfer phases of consecutive exchange operations can in each case be executed simultaneously.