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Method for simulating an open fault in a logic circuit comprising field effect transistors and simulation models for implementing the method
Method for simulating an open fault in a logic circuit comprising field effect transistors and simulation models for implementing the method
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机译:在包括场效应晶体管的逻辑电路中模拟开路故障的方法和用于实现该方法的仿真模型
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摘要
A method for simulating an open fault in a logic circuit comprising field effect transistors utilizes a simulation model which is employed and which takes the fault condition signal storage into consideration by way of an output stage. Given the appearance of a fault- influence signal at the output of a simulation stage, this maintains the through- connection of the signal which appeared immediately before the influenced signal to the simulation model output. In order to take reloading events in the real logic circuit into consideration, this through-connection is canceled after a prescribable time interval.
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