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Maruchipurosetsusashisutemuniokerumemoriakusesuseigyohoshiki

机译:多专业理论系统中的内存访问控制

摘要

PURPOSE:To make efficient access control by comparing an ID of access requesting unit and an ID of access requesting unit selected directly before in other system when an access request is selected by priority control of a memory controller of own system, and suppressing the memory access of own system when they coincide. CONSTITUTION:Priority controlling circuits 16a and 17a make priority control on an access request from subsystems 10, 11 of own system and other system, and select a unit of the highest priority and output the ID, and permit access to main memories 18, 19 of own system. Comparators 16c and 17c compares the result of selection by priority control of MCU of other system 1 clock before and the result of selection by priority control of MCU of own system in the present clock. Outputs of comparators 16c and 17c are made effective only when ID outputted from priority control circuits 16a and 17a is that of own system unit, and when an effective coincidence output is generated, starting of access to the main memory of own system is suppressed in the system.
机译:目的:通过比较自己系统的存储控制器的优先级控制选择访问请求时,通过比较访问请求单元的ID和在其他系统中之前直接选择的访问请求单元的ID,进行有效的访问控制,并抑制对存储器的访问当它们重合时组成:优先级控制电路16a和17a对来自本系统和其他系统的子系统10、11的访问请求进行优先级控制,并选择优先级最高的单元并输出ID,并允许访问主存储器18、19自己的系统。比较器16c和17c比较当前时钟中通过其他系统1时钟的MCU的优先级控制选择的结果和通过本系统的MCU的优先级的优先级选择的结果。仅当从优先级控制电路16a和17a输出的ID是本系统单元的ID时,并且当产生有效的同时输出时,比较器16c和17c的输出才有效。在本实施例中,抑制了对本系统主存储器的访问的开始。系统。

著录项

  • 公开/公告号JPH0234062B2

    专利类型

  • 公开/公告日1990-08-01

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP19850089769

  • 发明设计人 TOYOKI NORYUKI;

    申请日1985-04-25

  • 分类号G06F12/00;G06F9/52;G06F13/18;G06F15/16;G06F15/177;

  • 国家 JP

  • 入库时间 2022-08-22 06:22:24

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