PURPOSE:To increase a processing speed by providing an array cache momory arranged in two dimensions wherein memory elements more than processor elements in a processor array. CONSTITUTION:An address multiplexer 7 selects and applies an address to a memory body 4 during a readout period. Then read data is transferred to and stored in the register 6 of a destination memory element or a processing element in the array processor. On the other hand, the address multiplexer 7 selects and applies a write address to the memory body 4 during a write period. At this time, a write signal is fed and the data stored in the register 6 during the last readout period is written in the specified address of the memory 4. A data multiplexer 5 is controlled systematically as to the respective memory elements of the array cache memory 3 to shift and transfer simultaneously data on the two-dimensional plane of the array cache memory in some specific direction.
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