Arrangement for reducing the piezo effects in a semiconductor material that contains at least one piezo effect-sensitive electric device, and method of making the same

摘要

1. An arrangement for reducing piezoelectric effects in at least one piezoelectric effect-sensitive electrical component (3) arranged in a semiconductor material (1), wherein the semiconductor material (1) is mounted along a support surface on a carrier material (2), characterised in that only a part of the semiconductor material (1) is occupied by the piezoelectric effect-sensitive electrical component (3) or the piezoelectric effect-sensitive electrical components (3) and that there is an intermediate space (4) between said part of the semiconductor material (1) and the associated part of the carrier material (2).