I (UP ARROW) 2 (UP ARROW) L LOGIC GATE

摘要

The invention relates to an I2L logic gate which exhibits a multiplicity of outputs (A1-A13) by subdivision into part-gates (TG1-TG4), each part-gate being formed from a PNP injection transistor and an NPN multiple-collector switching transistor. The individual part-gates are arranged in such a manner that the total logic gate forms a linear cascaded arrangement. IMAGE