Technique for placement of pipelining stages in multi-stage datapath elements with an automated circuit design system

摘要

According to a method for designating the locations of pipelining stages in multi-stage datapath elements, the delay associated with each stage of the multi-stage element is estimated. Then, beginning with a designated stage of the multi-stage element, the estimated delays for the individual stages are added to obtain an accumulated delay time. Whenever the accumulated delay time exceeds a desired cycle time, a pipelining stage is inserted into the multi-stage element prior to the stage which caused the accumulated delay time to exceed the desired operating cycle time. Then, the method is continued for succeeding stages in the datapath element until all of its stages have been accounted for.