Passivation of semiconductor wafers to minimise stress and thin film cracking - using 1st layer which after planarisation encloses the metallisation pattern and further layers to provide specific protection

摘要

In the process, as a last step the wafers have the definition of a pattern in the upper metalisation layer (64). Then, an insulating dielectric layer (66), pref. undoped Si02, is metal stripe. This layer is then planarised, pref. using a chemical or mechanical polishing process, until a suitable thickness remains which encloses the metal pattern. A planar layer (70) is then deposited on top of a material which gives adequate mechanical, chemical and humidity protection pref. Si3N4 deposited by plasma enhanced CVD using SiH4 and NH3. Also claimed is the planarisation using photoresist in an etchback process or a reflow process. USE/ADVANTAGE - The process avoids the formation of a profile of the passivation layer which can lead to thin film cracking. It also ensures that an even coating of the metallisation layer occurs which improves the resistance to moisture ingress.