首页> 外国专利> Character and signal generator for detecting keyboard disconnected condition generated by an interrupted booting process and generating signal indicating that keyboard is now coupled thereto

Character and signal generator for detecting keyboard disconnected condition generated by an interrupted booting process and generating signal indicating that keyboard is now coupled thereto

机译:字符和信号发生器,用于检测由中断的引导过程产生的键盘断开状态,并产生指示键盘现在已耦合到其上的信号

摘要

A signal generator for generating an F1 keyboard keystroke and a clock signal responsive to expiration of a time delay sufficient for a computer to which the generator is coupled to partially complete a "boot" process to a point where the computer has detected a "keyboard disconnected" condition and entered a "wait" state. The generated F1 keystroke provided to the computer by the signal generator indicates to the computer that a keyboard is now coupled to the computer, allowing the computer to continue the "boot" process.PPIn the embodiment disclosed, a time delay circuit provides an enabling signal after expiration of the time delay to a latch circuit, a clock signal generator, and a coupling circuit. The output of the latch circuit initially enables loading of a 12-bit shift register with data from a plurality of switches and thereafter switches the mode of the shift register from "load" to "shift. " The clock signal clocks the data from the shift register, and the coupling circuitry couples the clock signal and the data from the shift register to the computer as it is clocked from the shift register. Termination circuitry detects the end of the data from the shift register and provides a disabling signal to the clock generator, ending the data stream upon occurrence of the last data pulse.
机译:响应于时间延迟的到期而产生F1键盘击键的信号发生器和时钟信号,该时间延迟足以使耦合到该发生器的计算机部分完成“启动”过程,直到计算机检测到“键盘断开连接”条件并进入“等待”状态。由信号发生器提供给计算机的所产生的F1击键向计算机指示键盘现在已经连接到计算机,从而允许计算机继续“引导”过程。在所公开的实施例中,时间为延迟电路在时间延迟到期后将使能信号提供给锁存电路,时钟信号发生器和耦合电路。锁存电路的输出最初使来自多个开关的数据加载到12位移位寄存器中,然后将移位寄存器的模式从“加载”切换为“移位”。时钟信号为来自移位的数据计时寄存器,并且耦合电路将时钟信号和数据从移位寄存器耦合到计算机,该数据是从移位寄存器计时的。端接电路检测来自移位寄存器的数据结尾,并向时钟发生器提供禁用信号,在最后一个数据脉冲出现时结束数据流。

著录项

  • 公开/公告号US5222228A

    专利类型

  • 公开/公告日1993-06-22

    原文格式PDF

  • 申请/专利权人 CYBEX CORPORATION;

    申请/专利号US19900627755

  • 发明设计人 ROBERT R. ASPREY;

    申请日1990-12-14

  • 分类号G06F3/023;

  • 国家 US

  • 入库时间 2022-08-22 04:58:12

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