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CLOCK SIGNAL DISTRIBUTION WIRING METHOD AND BLOCK DIVISION METHOD FOR CLOCK SIGNAL DISTRIBUTION WIRING
CLOCK SIGNAL DISTRIBUTION WIRING METHOD AND BLOCK DIVISION METHOD FOR CLOCK SIGNAL DISTRIBUTION WIRING
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机译:时钟信号分配布线的时钟信号分配布线方法和块分割方法
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摘要
PURPOSE: To minimize skew and to distribute and wire clock signals by dividing elements for receiving the supply of clocks into plural blocks, arranging delay inside the block and performing wiring so as to equalize the delay among the respective blocks. ;CONSTITUTION: A wiring graph whose nodes includes the entry points of respective element/element groups (blocks) is prepared. The pair of the element/ element groups is decided while repeating a processing for supplying a division line so as to minimize a delay difference in the wiring graph, so as to equalize the delay from a route driver to the entry points of the respective blocks based on the graph and a tree structure is prepared on the graph. A tree route is obtained bottom up along the tree and the wiring is performed while obtaining branching points so as to equalize the delay on a down stream side.;COPYRIGHT: (C)1994,JPO
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