首页> 外国专利> CLOCK SIGNAL DISTRIBUTION WIRING METHOD AND BLOCK DIVISION METHOD FOR CLOCK SIGNAL DISTRIBUTION WIRING

CLOCK SIGNAL DISTRIBUTION WIRING METHOD AND BLOCK DIVISION METHOD FOR CLOCK SIGNAL DISTRIBUTION WIRING

机译:时钟信号分配布线的时钟信号分配布线方法和块分割方法

摘要

PURPOSE: To minimize skew and to distribute and wire clock signals by dividing elements for receiving the supply of clocks into plural blocks, arranging delay inside the block and performing wiring so as to equalize the delay among the respective blocks. ;CONSTITUTION: A wiring graph whose nodes includes the entry points of respective element/element groups (blocks) is prepared. The pair of the element/ element groups is decided while repeating a processing for supplying a division line so as to minimize a delay difference in the wiring graph, so as to equalize the delay from a route driver to the entry points of the respective blocks based on the graph and a tree structure is prepared on the graph. A tree route is obtained bottom up along the tree and the wiring is performed while obtaining branching points so as to equalize the delay on a down stream side.;COPYRIGHT: (C)1994,JPO
机译:目的:通过将用于接收时钟源的元件划分为多个块,在块内安排延迟并进行布线,以使各个块之间的延迟相等,以最大程度地减少歪斜并分配和布线时钟信号。 ;构成:准备一个布线图,其节点包括各个元素/元素组(块)的入口点。在重复提供分割线的处理的同时确定一对元件组,以最小化布线图中的延迟差,从而均衡从路径驱动器到各个块的入口点的延迟。在图上创建树结构。沿着树的底部向上获得一条树路线,并在进行布线的同时获得分支点,以均衡下游侧的延迟。;版权:(C)1994,JPO

著录项

  • 公开/公告号JPH06282603A

    专利类型

  • 公开/公告日1994-10-07

    原文格式PDF

  • 申请/专利权人 TOSHIBA CORP;

    申请/专利号JP19930070298

  • 发明设计人 TAKANO MIDORI;

    申请日1993-03-29

  • 分类号G06F15/60;H01L21/82;

  • 国家 JP

  • 入库时间 2022-08-22 04:49:50

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