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X. 25/X. 75 LAYER 2 PROCESSOR

机译:X. 25 / X。 75第2层处理器

摘要

PURPOSE:To improve the date link processing reliability of a device which performs the termination processing of the X. 25 and X. 75 layers 2 by preventing the omission and the double feed of an I frame when a link is decided again after the occurrence of a fault. CONSTITUTION:A CPU 4 of a layer 2 processor 1 controls a layer 2 terminating circuit 3 to add the signal identification sequence numbers counted in a memory 5 for transmission of an I frame and to sample the signal identification sequence numbers added from a device of the opposite party for reception of the I frame. Then the CPU 4 receives a global address frame that designated a specific address from the device of the opposite party and then reads the signal identification sequence number out of an information field to sent again the I frame to which the read sequence number is assigned.
机译:目的:通过在发生X.25和X.75层2的情况下再次确定链接时避免I帧的遗漏和双重馈送,来提高执行X.25和X.75层2终止处理的设备的日期链接处理可靠性。一个错误。组成:第2层处理器1的CPU 4控制第2层终端电路3,将在存储器5中计数的信号标识序列号相加,以传输I帧,并对从I / O设备中添加的信号标识序列号进行采样对方接收I帧。然后,CPU 4从对方的设备接收指定了特定地址的全局地址帧,然后从信息字段中读取信号识别序列号,以再次发送分配了读取的序列号的I帧。

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