Multiplexing / demultiplexing of subscriber connection / terminal equipment in an optical cable television (CATV) network

摘要

The present invention relates to a circuit for implementing a multiplexing / demultiplexing function for data transmission between a distribution center and a subscriber in an optical CATV network, A framer (14) receiving a clock signal and receiving a clock signal from the framer (14) to generate a frame, First and second address generating means (13,25) for generating an enable signal and providing a clock signal to the first and second synchronization means (11,12) A scrambler 15 for receiving a clock and extracting a clock from a receiver, and a scrambler 15 for receiving a clock signal and an output signal of the framer 14 to detect a bit error through a parity check to output a bit error detection signal to the framer 14, Provide as A multiplexer circuit (1) having a parity generating means (16) for receiving a clock signal, a refresher (21) for receiving a clock signal and enabling recovery of error data, A descrambler 22 for descrambling the received address signal from the address decoder 25 and outputting an output obtained by subtracting the address signal from data from the outside, CIB detecting circuit means 23 for detecting a channel discrimination bit (CIB) value inserted in the CIB detecting circuit means 23, hold signal generating circuit means 24 for generating a holding signal by using the detection value from the CIB detecting circuit means 23, An address bit signal and a clock signal from the second address generating means 25 and a subtraction operation signal of an output of the descrambler 22 and an external data, A channel classification circuit means (26) for classifying the positions of the maintenance signals received by the channel classification circuit means (26), a parity bit and a clock signal of the channel classification circuit means A parity generating and checking means 27 for generating a parity error signal when a channel classification signal of the channel classification circuit means 26 and an address signal from the second address generation means 25 are received, And a demultiplexing circuit (2) having two inverse synchronization means (28, 29).