Digital integrator with reduced circuit area and analog-to-digital converter using same

摘要

The digital integrator 22 reduces the circuit area and power consumption by performing two stage integration on a decade with only one adder 51. The transfer function of the two stage integrator in the Z-domain may be expressed as H (z) = (1 / (1-z ⁻¹ )) ² . The enlarged transfer function may be expressed as H (z) = (1 / (1-2z ⁻¹ + z ⁻² )). Conversely, Z-strain yields the equation y [n] = X [n] + 2y [n-1] -y [n-2], which is a single adder 51 and two delays 52, 55 And 54). In one embodiment, the three stage integrator 22 within the single adder circuit 91 by multiplexing the required sum of the two stage integrator and the sum required for one stage integration in the adder circuit 91 over time. It can also be executed.