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Multiplying system based on the Booth's algorithm and generating a positive or negative product in response to a mode signal

机译:基于Booth算法的乘法系统,并响应模式信号生成正或负积

摘要

A multiplying system based on the Booth's algorithm, comprises a Booth's decoder having a first input receiving a multiplier "Y" and a second input receiving a mode signal designating either a first multiplication of "X×Y" (where "X" is a multiplicand) or a second multiplication of "-X×Y". The Booth's decoder generates a Booth's decoded value and a sign selection signal to a partial product generation circuit which also receives the multiplicand "X", so that the partial product generation circuit generates either a first partial product of "X. times.Y" or a second partial product of "-X×Y" in accordance with the sign selection signal. An output of the partial product generation circuit is summed by a partial product summing circuit, and an output of the partial product summing circuit is added to a value "A" stored in an output register by an arithmetic unit. Thus, the accumulating multiplication "A=A.+-.X×Y" can be executed in the same hardware without using a circuit for sign-inverting the output of the partial product summing circuit.
机译:一种基于布斯算法的乘法系统,包括布斯解码器,该解码器的第一输入接收乘数“ Y”,第二输入接收模式信号,该信号指定第一乘积“ X×Y”(其中“ X”是被乘数) )或“ -X×Y”的第二个乘法。布斯的解码器生成布斯的解码值和符号选择信号给部分乘积生成电路,该部分乘积生成电路也接收被乘数“ X”,从而部分乘积生成电路生成“ X.Y.”的第一部分乘积或根据符号选择信号,第二部分乘积为“ -X×Y”。通过部分乘积求和电路将部分乘积生成电路的输出相加,并且通过运算单元将部分乘积求和电路的输出与存储在输出寄存器中的值“ A”相加。因此,可以在相同的硬件中执行累加乘法“ A = A.±X×Y”,而无需使用用于对部分乘积求和电路的输出进行符号反转的电路。

著录项

  • 公开/公告号US5303178A

    专利类型

  • 公开/公告日1994-04-12

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号US19920830400

  • 发明设计人 YASUSHI OZAKI;

    申请日1992-01-31

  • 分类号G06F7/52;

  • 国家 US

  • 入库时间 2022-08-22 04:31:56

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