Video images decoder architecture for implementing a 40 ms processing algorithm in high definition televisions

摘要

A video image decoder architecture for implementing a processing algorithm in the 40-ms mode on high-resolution TV sets, of a kind adapted to handle TV signals being received on respective transmission channels (A,C), comprises:a video signal demultiplexer (12) being input said transmission channels (A,C);respective processing blocks (13,14) for separately handling the signals from each of the channels (A,C) and comprising,a video image format converter (15),a local memory (17) connected after the converter, andat least one median filter (25) and one systolic filter (27) cascade connected after said memory for restoring, by interpolation, signal samples related to successive lines of the video image;and a summing node (11) for adding together the outputs from each processing block (13,14) by obtaining a time mean between restored samples (Ai,Ci) of the channels (A,C). This architecture allows a drastic reduction in the number of memories required for processing the restore algorithm, as well as a reduction in overall silicon area for the system, and accordingly, the possibility of having the whole 40-millisecond processing portion integrated to a single chip.