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Programmable logic device having fast programmable logic array blocks and a central global interconnect array
Programmable logic device having fast programmable logic array blocks and a central global interconnect array
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机译:具有快速可编程逻辑阵列模块和中央全局互连阵列的可编程逻辑器件
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摘要
A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.
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