SEQUENTIAL WORK LINE CONTROL TYPE SEMICONDUCTOR MEMORY UNDER REFRESH MODE

摘要

PROBLEM TO BE SOLVED: To obtain sequential work line control type memory under refresh memory in which the refresh cycle is reduced without degrading chip performance by activating a large number of word lines sequentially in one cycle. ;SOLUTION: When a clock control section 10 makes a transition to refresh mode, an enable signal is generated from a refresh control section 12 and a refresh counter 22 is enabled. During one cycle of row address strobe signal RAS, the row address having the output from counter 22 increases sequentially and the output is fed from a row address buffer 16 to a row decoder 18. Consequently, the number of word lines being selected during one cycle of the signal RAS increases sequentially and the peak current does not increase thus sustaining the chip performance. Furthermore, since the number of word lines to be enabled is increased, refresh cycle can be reduced.;COPYRIGHT: (C)1997,JPO