PURPOSE:To accelerate a picture processing without applying burden to a CPU by using a circuit such as a shift register, etc. to execute a gradation processing. CONSTITUTION:A first shift register group 16 is provided to store data composed of an (m) number of rows and an (n) number of columns, and a numerical value converting means 12 is provided to convert a numerical value by using a parameter applied in advance for data to be successively parallelly outputted from this first shift register group. Then, an adder 13 is provided to add the data, which numerical values are converted, successively for the prescribed number of times, and a second shift register group 14 is provided to successively store the outputs of the adder as data after the gradation processing. For the data to be outputted by the shift operation of the first shift register group 16, the numerical values are converted by the numerical value converting means 12 and these data are added by the adder 13. Thus, the arithmetic of the gradation processing can be executed without interposing the CPU.
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