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ARCHITECTURES AND METHODS FOR DIVIDING PROCESSING TASKS INTO TASKS FOR A PROGRAMMABLE REAL TIME SIGNAL PROCESSOR AND TASKS FOR A DECISION-MAKING MICROPROCESSOR INTERFACING THEREWITH
ARCHITECTURES AND METHODS FOR DIVIDING PROCESSING TASKS INTO TASKS FOR A PROGRAMMABLE REAL TIME SIGNAL PROCESSOR AND TASKS FOR A DECISION-MAKING MICROPROCESSOR INTERFACING THEREWITH
Method for dividing a processing task into tasks for a programmable real time signal processor means and tasks for a host processor means, wherein said signal processor means and said host processor means each include means for interfacing with each other, and said signal processor means includes program memory means and data memory means, said method comprising: describing and representing said processing task for said signal processor means with a plurality of high level signal processing functional block means and a plurality of connections therebetween, each functional block means having a name, and a plurality of said functional block means having parameters; providing a signal processor cell library means containing code representing a plurality of said high level signal processing functional block means and containing named cell specific variable requirements; analyzing, scheduling, and compiling said code with a signal processor scheduler means, and providing program code for the program memory of the signal processor means, data code for the data memory of the signal processing means, and a correspondence table between signal processor memory locations and said named cell variables and parameters of said functional blocks; providing said correspondence table or a translation thereof to the compiler of the host processor means for compilation.
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