DUAL I/O LOGIC FOR HIGH VOLTAGE CMOS CIRCUIT USING LOW VOLTAGE CMOS PROCESSES

摘要

CMOS transistor logic circuitry (20/22) is permitted to operate at higher power supply voltages while retaining lower voltage processing geometries by providing each input signal as dual input signals (28/36) that track each other within two different voltage ranges. A shield voltage (40/42) is provided approximately midway between the uppermost and lowermost power supply voltages (34/26). The first input signal (28) ranges between the lowermost power supply voltage (26) and the shield voltage (40), and the second input signal (36) ranges between the shield voltage (40) and the uppermost power supply voltage (34). The first and second input signals (28/36) drive the gates of n-channel and p-channel CMOS switching transistors (24/32), respectively, the drain terminals of which are coupled to first and second output terminals (30/38), respectively. N-channel and p-channel shield transistors (44/46) are connected in series between the first and second output terminals (30/38), and have their gate terminals coupled to the shield voltage (40/42).